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74AUP2G14DW-7 image
74AUP2G14DW-7 image


Diodes Incorporated
RoHS RoHS compliant
Package 6-TSSOP, SC-88, SOT-363
Category Logic - Gates and Inverters / Logic - Gates and Inverters
Description R-PDSO-G6 74AUP Tape & Reel (TR) AUP/ULP/V logic gate circuit 5.4ns @ 3.3V 30pF 1.1mm 4mA 4mA 3.6V
Buying Options
Total Price: USD $0.84
Unit Price: USD $0.168708
≥5 USD $0.168708
≥50 USD $0.13817
≥150 USD $0.125093
≥500 USD $0.108761
Inventory: 2970
Minimum: 5

Technical Details


Mount Surface Mount
Mounting Type Surface Mount
Package / Case 6-TSSOP, SC-88, SOT-363
Weight 6.010099mg


Height Seated (Max) 1.1mm


RoHS Status ROHS3 Compliant


Operating Temperature -40°C~125°C
Packaging Tape & Reel (TR)
Published 2013
Series 74AUP
JESD-609 Code e3
Part Status Active
Moisture Sensitivity Level (MSL) 1 (Unlimited)
Number of Terminations 6
Terminal Finish Matte Tin (Sn)
Technology CMOS
Voltage - Supply 0.8V~3.6V
Terminal Position DUAL
Terminal Form GULL WING
Peak Reflow Temperature (Cel) NOT SPECIFIED
Number of Functions 2
Supply Voltage 1.2V
Terminal Pitch 0.65mm
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
JESD-30 Code R-PDSO-G6
Supply Voltage-Max (Vsup) 3.6V
Supply Voltage-Min (Vsup) 0.8V
Number of Circuits 2
Propagation Delay 5.4 ns
Quiescent Current 500nA
Turn On Delay Time 37.3 ns
Family AUP/ULP/V
Number of Inputs 1
Current - Output High, Low 4mA 4mA
Logic Type Inverter
Max Propagation Delay @ V, Max CL 5.4ns @ 3.3V, 30pF
Logic Level - Low 0.1V ~ 0.88V
Logic Level - High 0.6V ~ 2.29V

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